1. Field of the Invention
The present invention generally relates to clock-data recovery.
2. Description of Related Art
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “signal,” “clock,” “half-rate,” “edge (of clock),” “binary,” “vertical eye opening,” “binary phase detector,” “filter,” “voltage-controlled oscillator,” “ternary,” “current-mode,” “charge-pump,” “ADC (analog-to-digital converter).” Terms and basic concepts like these are apparent to those of ordinary skill in the art and thus will not be explained in detail here.
A prior art half-rate clock-data recovery circuit is a circuit that receives a signal comprising a stream of serial binary symbols of a symbol period Ts The circuit establishes a 4-phase recovered clock that is aligned with a timing of the received signal, wherein a period of the 4-phase recovered clock is 2·Ts i.e., twice of the symbol period Ts.
As depicted in FIG. 1A, a prior art half-rate clock-data recovery circuit 100 comprises: a half-rate phase detector 110 for receiving the received signal and the 4-phase recovered clock. The half-rate phase detector outputs a phase error signal 111 (which is usually a current-mode ternary signal). A loop filter 120 receives the phase error signal 111 and outputs a control signal 121 (which is usually a voltage signal). A quadrature clock generator 130 (which is usually a voltage-controlled oscillator) receiving the control signal 121 and outputs the 4-phase recovered clock. The 4-phase recovered clock is established in a closed-loop manner to track a timing of the received signal. Half-rate clock-data recovery circuit 100 is well known in prior art and thus not described in detail here.
An exemplary waveform of a prior art half-rate clock-data recovery circuit, as observed by using an oscilloscope, is shown in FIG. 1B. The received signal, when observed using an oscilloscope, comprises a stream of binary symbols that exhibits an “eye” pattern. The recovered clock, on the other hand, is a 4-phase square wave, comprising phase 0, phase 1, phase 2, and phase 3. The binary symbols alternate between an even symbol and an odd symbol. An edge (i.e., rising edge) of phase 0 aligns with a transition from an odd symbol to an even symbol (e.g., edges 150 and 154); an edge (i.e., rising edge) of phase 1 aligns with a center of an even symbol (e.g., edges 151 and 155); an edge (i.e., rising edge) of phase 2 aligns with a transition from an even symbol to an odd symbol (e.g., edges 152 and 156); and an edge (i.e., rising edge) of phase 3 aligns with a center of an odd symbol (e.g., edges 153 and 157). Once the edges of phase 0 and phase 2 are properly aligned by using a clock-recovery circuit, the even symbols can be detected by sampling the received signal in accordance with the edge of phase 1, and the odd symbols can be detected by sampling the received signal in accordance with the edge of phase 3.
There is a problem associated with the prior art half-rate clock-data recovery circuit 100. An “eye” of a received signal might be assymmetrical, and also an “eye” of an even symbol may be different from an “eye” of an odd symbol of received signal. As illustrated in another exemplary timing diagram shown in FIG. 1C, a symbol period Ts1 of an even symbol is different from a symbol period Ts2 of an odd symbol, due to a duty-cycle distortion. Moreover, an “eye” of an odd symbol is assymmetrical. In this case, the prior art half-rate clock-data recovery circuit 100 may not work well because there is no guarantee each of the four phases of the four-phase recovered clock is optimally timed, with respect to the received signal.
What is desired is a half-rate clock-data recovery circuit that can overcome the aforementioned problems.